Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

In a wireless RF transceiver, the Phase Locked Loop (PLL) frequency synthesizer is used as a stable local oscillator for the up and down frequency conversion between the baseband and RF signals. This sub-system can consume one third of the total power consumed by the whole transceiver. The dual modulus prescaler consumes more than one third of the power used by the PLL. In the Giga-Hertz range, two types of CMOS circuits namely, true single phase clock (TSPC) and extended true single phase clock (E-TSPC) are used for designing frequency prescalers, where the TSPC consumes less power at the expense of lower speed. Based on our study, two new low power and improved speed TSPC 2/3 prescalers are proposed and silicon-verified. Compared with the conventional TSPC architectures designed under the same 0.18μm CMOS technology at supply voltage of 1.8V, both proposed 2/3 prescalers improve the operating speed by 1.3 times up to 5 GHz. The extremely low power consumption is achieved by radically decreasing the sizes of transistors and optimizing the embedded logic gates around the D flip-flop (DFF) as in the Design I prescaler, and furthermore allowing the DFF to sleep when it is not in use as in the Design II prescaler. The accompanying table shows a reduction of the power consumption by almost 50% in Design I and 67% in Design II when compared to other state-of-the-art designs. A divide-by-32/33 dual modulus prescaler has also been implemented with the Design-II 2/3 prescaler using a Chartered 0.18μm CMOS technology, and is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.

A Possible Reality on battery-free Low-power Portable Electronics

The idea of harvesting electromagnetic energy and converting it to useful DC power is not new and has been researched in the context of high power beaming in the 1950s. However, due to the concern of biological hazards, high power wireless transmissions are regulated by the telecommunication authorities. Because the transmitted power is restricted, harvesting radiated electromagnetic energy from the wireless transmission and converting it to a DC voltage comparable to a standard battery is a challenging task. The maximum converted DC voltage using the conventional harvesting technique, such as rectenna (antenna-rectifier combined circuit) arrays, could achieve at most a few hundred mV even with carefully designed matching between the antenna and the diode, due to the inherent losses in the rectification process. This voltage level is only good enough for extremely low power sensors but is insufficient for most practical electronic devices that operate at 1 V and above. We have realized a novel electromagnetic energy harvesting concept through a working circuit. The circuit designed and fabricated is capable of converting low power electromagnetic energy to a DC voltage level of more than 1.5 V in a short time. The attached figures show the schematic of our circuit and the experimental output voltage of our circuit when it is placed in the open air with an EM source of 80MHz and 0.52W output power at 3m away from the circuit.

Low-Jitter Frequency Multiplier for High-Speed Mixed-Signal Chips

Timing jitter is an important design parameter for most of the high-speed mixed-signal circuits and systems. A low-jitter frequency multiplier is one of the critical components for an integrated system design. Applications such as precision clock for high-speed data converters and clock generator for microprocessor/microcontroller based designs are good examples. Conventional phase-locked loop (PLL) clock multiplier architecture suffers from the jitter accumulation effect due to its narrow loop bandwidth required for the loop stability. Although improved jitter performance can be achieved through the use of delay locked loop (DLL) clock multiplier architecture, it still suffers from jitter accumulation in the cascade of the delay chain. An innovative approach is explored in the research. To circumvent the problem, the cascade structure of the delay chain, that defines the clock edges of the crystal oscillator for frequency multiplication, will be replaced with a passive RC polyphase filter having the low thermal noise characteristic. To reduce the static phase errors arising from the polyphase filter and devices mismatch effect, an analog phase error calibration circuit that is independent of delay sensing mismatch, is employed. The circuit technique leads to a new polyphase filter (PPF) clock multiplier. The preliminary experimental results of the prototype have shown that the unconventional architecture exhibits low-power low-jitter performance metrics, suggesting the potential of work for high-speed mixed-signal
chip design.